Hardware Verification in Python – An Abstract


This section, “Hardware Verification in Python” is part of “Hardware Verification Languages”, which again belongs to the volume of “Verification IP & IP Core Verification” of the book family titled “Semiconductor IP Core – Not Just Design”.

This chapter treats some of the key Python methodologies, tools, packages and libraries involved in the verifications of IC and IP core design process, including the following chapters:

Pure Python - Why Python? How to use Python for verification (testbenches)?

Cocotb - (CO-routine and CO-simulation of Testbench) possibly the de facto Python design verification methodology

MyHDL - A Python based hardware description language, also with verification functionality

PyUVM – a Python implementation of the UVM using cocotb

UVM Python – UVM port to Python 

PyMTL - A Python framework for open-source hardware modeling, generation, simulation, and verification

PyHVL - A Python verification tool

Constraints and Coverage	
	PyVSC Package: SystemVerilog-style constraints and coverage in Python
	YosysHQ/MCY - Mutation cover with Yosys	

Front-End Driver Program
	YosysHQ/SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows 
	
Symbolic Model Checking	
	COSA: Integrated verification for agile hardware design	

Metaprogramming Hardware Verification Components
	FAULT: A Python embedded domain-specific language for metaprogramming portable hardware verification components	

Python Prototyping
	VPSim - Fast virtual prototyping for embedded computing systems design and exploration	
	pyrtl - A pythonic approach for rapid hardware prototyping and instrumentation	
	
Python Emulation	
	ICEMU - Emulate integrated circuits in Python	
	AMIQ OFC - Open-source framework for co-emulation using PYNQ

Python Simulation
	PyCPU simulator	- CPU Simulator written in Python
	PyOPUS - a Python library for interfacing to various simulators
	AHKAB -	a SPICE-like electronic circuit simulator written in Python
	PySPICE - Simulate electronic circuit using Python and the NGSpice / Xyce simulators
	cosimtcp - Co-simulation of HDL using Python and Matlab over TCL TCP/IP socket in Xilinx Vivado and Modelsim tools	
	PyVHDL: A hardware simulation environment integrating Python and VHDL	
	FPGA_HW_SIM_FWK - FPGA hardware simulation framework


Python as the most popular programming language is the natural choice of hardware verification language (HVL), particularly for the newcomers of the IC design sector, who are not so much involved in more demanding HVLs such as SystemVerilog, Verilog, SystemC, e, VHDL etc. Python is easy to learn (chances are you know it already), yet Python is still powerful enough to meet some of the key verification requirements. Versatility and ability to cope with almost any design philosophy is the distinguishing mark of Python, therefore it is not surprising that it has finally approached to hardware design.Hardware modules are modeled as Python functions with wrapping decorators that return sets of generators. Thus, the semantics and structure of Python functions are used to support features such as arbitrary hierarchies of
components, named port association, etc...

Yet production verification engineers are not aiming to replace UVM with Python. There will always be many clever things that UVM can do that Python cannot (easily). The purpose of Python development and usage around verification is to plug the holes in mainstream verification methodologies. For stupid tests and to support designers running their own verification. To speed up standard verification flows and to support silicon bringup test development. etc etc.

This 500-page long introductory material will introduce readers to the major Python methodologies, systems, packages and libraries dealing with the hardware verification needs, incl also prototyping, emulation and simulation. After reading, readers will become familiar with historic notes, key features, installation & configuration, usage, verification samples and results as well as their applications in the IC design and verification sectors. I will leave benchmarking to my readers, as the technology is still maturing and it’s still a bit too early to say who is the best among dozens of Python-based verification systems.

For details about the chapter contact the author for a complete text.